Page 8 Design Specification
AN 311: Standard Cell ASIC to FPGA Design Methodology and Guidelines © April 2009 Altera Corporation
available is device dependent. Stratix devices provide fast regional clocks in addition
to the global low-skew resources. Similarly, StratixII, StratixIII, and StratixIV devices
provide a hierarchical clocking structure consisting of global clocks (GCLKs), regional
clocks (RCLKs), and peripheral clocks (PCLKs). You can use a combination of these
low-skew signals to route clocks and other high fan-out signals in your design.
In addition to the clock networks described previously, Stratix GX series devices
feature separate clock distribution resources that connect directly to the clocking
resources of the device logic array. This architecture makes it flexible for reference
clock generation, clock domain translation, and support of multi-channel
functionality.
1 The Quartus II software turns off unused clock networks to reduce power dissipation
in the device. It can also disable unused portions of clock networks for Stratix II,
Stratix III, and Stratix IV devices, and can optimize the placement to minimize the
portion of the clock network used to further reduce power.
f For more information about regional clocks and fast regional clocks, refer to the Area
and Timing Optimization chapter in volume 2 of the Quartus II Handbook.
f For more information about the clocking resources such as GCLK, PCLK, and RCLK
within a specific device, refer to the appropriate device handbook.
For more information about clock tree synthesis and clock requirements, refer to
“Clock Tree Synthesis” on page 23.
Phase-Locked Loop (PLL) Requirements
Inserting PLL circuitry into a traditional standard cell ASIC device is typically a
manual process in which you instantiate special PLL blocks in the design. In the
Altera FPGA flow, you can create configurable PLLs with the MegaWizard
®
Plug-In
Manager, available in the Quartus II software. You can control PLL parameters such
as phase shift, clock switchover, and PLL bandwidth using the MegaWizard Plug-In
Manager. In the PLLs available in Altera devices, each output of the PLL can be
programmed independently, creating customizable clock frequencies that are
independent of other input or output clocks. Inherent jitter filtration and fine-grained
control of the configurable range help you generate the high-performance precision
clocks required in your system. The number of PLLs available in FPGA technology is
usually limited, whereas PLL quantities are virtually unlimited in traditional standard
cell ASIC technology.
f For more information about the number and type of PLLs supported in a specific
device, refer to the appropriate chapter on Clock Networks and PLLs in the Altera
device handbooks.
Clock Frequencies
The frequency at which your design is expected to operate is an important factor in
choosing the appropriate Altera FPGA for your design. The maximum frequency of
operation is affected by several factors, such as logic utilization, routing congestion,
and the speed grade of the chosen device.